Use of Particle Swarm Optimization to Design Combinational Logic Circuits

Erika Hernández-Luna developed a system to design combinational logic circuits using particle swarm optimization. In her work, she experimented with a matrix encoding to represent a circuit, and adopted both binary and integer encodings. The search engine of her program is a particle swarm optimizer that gives "rewards" to solutions that are both feasible and minimize the total number of gates of the circuit. The source code of this approach is available here.


For further information about this approach, please refer to:

1. Carlos A. Coello Coello, Erika Hernández Luna and Arturo Hernández Aguirre, A Comparative Study of Encodings to Design Combinational Logic Circuits Using Particle Swarm Optimization, in Ricardo S. Zebulum, David Gwaltney, Gregory Hornby, Didier Keymeulen, Jason Lohn and Adrian Stoica (editors), Proceedings of the 2004 NASA/DoD Conference on Evolvable Hardware, pp. 71--78, IEEE Computer Society, Los Alamitos, California, June 2004.
2. Carlos A. Coello Coello and Erika Hernández Luna, Use of Particle Swarm Optimization to Design Combinational Logic Circuits, in Andy M. Tyrell, Pauline C. Haddow and Jim Torresen (Eds), Evolvable Systems: From Biology to Hardware. 5th International Conference, ICES 2003, pp. 398--409, Springer, Lecture Notes in Computer Science, Vol. 2606, Trondheim, Norway, March 2003.