Fast hardware accelerators for the Tate pairing


Fast hardware accelerators for the Tate pairing

Dr. Jermie Detrey

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First introduced in cryptography by Menezes, Okamoto, & Vanstone (1993) and Frey & Rck (1994) as an attack on the discrete-logarithm problem over particular elliptic curves, pairings have since been used for constructive purposes in various cryptographic protocols such as short-signature schemes or identity-based encryption.  However, since the computation of those pairings relies heavily on finite-field arithmetic, their software implementation remains expensive and developing ad-hoc hardware accelerators is crucial.

In this talk, we will present a new coprocessor dedicated to the computation of the Tate pairing and designed so as to minimize the overall computation time.  A special emphasis will be put on the joint algorithmic and architectural rationales pertaining to this work.

Esbozo Curricular

Dr. Jrmie Detrey is a junior research scientist (CR2) at INRIA Nancy Grand-Est, in the CACAO  project-team at LORIA in Nancy, France. His research focuses on the hardware implementation of arithmetic circuits, where the term "arithmetic" covers:

    * Integer Arithmetic

    * Real arithmetic, such as fixed-point, floating-point or logarithmic number systems

    * Finite-field arithmetic as used in cryptography.

Dr. Jrmie Detrey has published several journal and international conference papers. He has won two times,  in 2007 and 2009, the best paper award in the premiere cryptographic conference Workshop on Cryptographic Hardware and Embedded Systems (CHES).